1. Field of Invention
The present invention relates to an analysis method, and more generally to an analysis method for a semiconductor device.
2. Description of Related Art
The fabrication process of a semiconductor integrated circuit (IC) chip is substantially divided into a front-end process and a back-end process. The front-end process is for fabricating an integrate circuit on a wafer. The back-end process is for packaging the wafer with the fabricated integrated circuit thereon. During the front-end and back-end processes, many structural tests and electrical property tests are performed frequently, so as to ensure the reliability and the yield of the chip. If these testing results show the wafer is abnormal, examples of the common testing apparatus include a scanning electron microscope (SEM), a transmitting electron microscope (TEM), and a focused ion beam (FIB) microscope, etc is used to fine the defects on the wafer.
Generally, TEM has been widely applied to perform the device failure analysis and the process evaluation for a semiconductor device with high density, so as to solve the problem of the yield and the device reliability. Before a TEM analysis is performed, a FIB microscope analysis process is usually conducted. The FIB microscope analysis process can provide an initial analysis result. On the other hand, the focused ion beam can thin the semiconductor device, so as to provide the transparency required for the electron beam of the subsequent transmitting electron microscope, and thus, a clear image is obtained.
However, the conventional method by using the FIB microscope and the TEM to perform the device failure analysis usually exists a problem. The conventional method cannot determine whether the observed abnormal region or the defect site is the real defect leading to the device failure.